HDMI 2.1 FEC Receiver (Tx)

Overview

The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2.1 specification.

Forward Error Correction is required to ensure glitch-free operation in Fix Rate Lane (FRL) mode, a packet mode introduced in HDMI 2.1. FRL allows for the use of Display Stream Compression (DSC) bitstream transport.

Solution for UHD Monitors, UHD TVs and Home Theaters, Pro AV, HDMI 2.1 Accessories

Key Features

  • HDMI 2.1 compliant
  • Reed-Solomon RS (255,251) FEC, 8-bit symbols
  • Supports 3-lane and 4-lane operation
  • Error counters included (Rx only)

Block Diagram

HDMI 2.1 FEC Receiver (Tx) Block Diagram

Applications

  • UHD monitors
  • UHD TVs & home theaters
  • HDMI 2.1 hubs & accessories
  • Professional video equipment

Deliverables

  • Encrypted RTL source code IP core
  • Functional and structural coverage reports
  • Comprehensive integration guide

Technical Specifications

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Semiconductor IP