HDLC/SDLC controller
Overview
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter.
Key Features
- Two separate receiver and transmitter interfaces.
- Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing
- Address recognition for receiver and address insertion for transmitter
- Two or one byte address field
- RC-16 and CRC-32 computation and checking
- Collision detect
- Byte alignment error detection
- Programmable number of bits for idle detection
- NRZI coding support
- Shared flags, shared zeros support
- Pad fill with flags option
- Transmitter clock generation
- 8-bit CPU interface
- Interrupt output for handling control flags and FIFOs’ filling
- Configurable core parameters Â
Applications
- http://www.dcd.pl/ipcore/102/d6802/
Deliverables
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Technical Specifications
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