HBM2E Memory Controller
Overview
HBM2E Memory Controller
Key Features
- Support Pseudo Channel mode with 64DQ per Pseudo Channel
- Support DFI1:2
- Support HBM Burst Length 4
- Support 4 High or 8 High HBM Devices
- Support only 1 AXI 4.0 ports with 64 / 128 / 256 / 512-bit data bus width for each Pseudo channel
- Support AXI 4.0 Standard
- Support only Parity Latency = 0 or 2
- Support Read DBI and Write DBI features
- Support Command/Address parity check feature
- Support DQ parity check feature
- Support both mode-1 and mode-2 DWORD remapping features
- Support HBM ECC function
- Support internal SRAM ECC function
- Consistent AXI read-after-write
- Support software programmable mapping from AXI address to SID, Bank-Group, Bank, Row, Column bits for user specific applications
- Support manual self-refresh and automatic self-refresh
- Support manual power-down and automatic power-down
- Support single bank refresh
- Support auto precharge
- Support memory BIST (Built In Self Test) function
Technical Specifications
Foundry, Node
TSMC
Maturity
Avaiable on request
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