HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
Overview
This is a high performance, small footprint HASH IP Core. It supports three HASH algorithms: MD5, SHA1, SHA256. A S/G DMA engine keeps the core running. Each hash engine has it’s own dedicated clock, which is independent of the main AXI clock.
Key Features
- Supports MD5, SHA1 and SHA256
- High Performance S/G DMA engine
- Fully AXI-4 compatible
- AXI-Light for register Interface
- Separate clocks for MD5, SHA and SHA256 engines and AXI interface
Benefits
- High Performance, small footprint
Deliverables
- Verilog Source Code
- Test bench
- Tech Support
Technical Specifications
Foundry, Node
any
Maturity
Silicon Proven
Availability
now
Related IPs
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- 1G/10G/25G/50G/100G Ethernet Switch IP Core - Efficient and Massively Customizable
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- ARINC818 controller Transmitter and Receiver IP core