GTS Ethernet FPGA Hard IP

Overview

Ethernet is ubiquitous across many markets and applications. The GTS Ethernet Intel FPGA Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet, compatible with the IEEE 802.3-2018 - IEEE Standard for Ethernet and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.

GTS Ethernet Hard IP Connects an Increasing Number of Devices

Agilex™ 5 devices serve a broad range of applications that require high performance, lower power, and smaller form factors. These characteristics make them ideal for midrange FPGA applications across the edge and core including:

  • Wireless and wireline communications
  • Video and broadcast equipment
  • Industrial applications
  • Test and measurement products
  • Medical electronics
  • Data center
  • Defense applications

The majority of the applications listed above utilize Ethernet connectivity and can leverage the EHIP to help accelerate their designs.

Features

Features

Description

Ethernet Rate/PMA combination

[Data Rate]-[Number of PMA]

  • 10GE-1
  • 25GE-1

PMA Type

ETH MAC and OTM support on CH3 and CH2 per bank. All channels support PCS Direct and FlexE mode.

Flexible Configuration

  • Media Access Control (MAC), Physical Coding Sublayer (PCS), and Physical Medium Attachment (PMA)
  • PMA with optional Forward Error Control (FEC)
  • PCS and PMA with optional FEC supports:
    • Ethernet for Optical Transportation Network (OTN)
    • Flexible Ethernet (FlexE)

Client interface

  • MAC Avalon® streaming interface
  • PCS Direct Mode
    • Media Independent Interface (MII)
    • PCS66 – Supports OTN and FlexE mode.

Forward error correction (FEC)

  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 Reed-Solomon (RS) RS (528,514) (CL91)

Precision Timing and Link Training

  • Support for the 1588 Precision Time Protocol (PTP)
  • Support for Auto-negotiation (AN) and Link training (LT)

Block Diagram

GTS Ethernet FPGA Hard IP Block Diagram

Technical Specifications

×
Semiconductor IP