GSMC 0.13um LP IO Library
Overview
GSMC 0.13um LP process 1.2v/3.3v Generic IO library
Key Features
- GSMC 0.13um LP Logic 1P7M Salicide 1.2V/3.3V Process.
- 3.3V I/O, 1.2V Core, 5V Tolerant.
- Both Inline and Stagger Compatible IO Pads.
- Configurable Input-Output and Skew Rate Control.
- Robust ESD (>2000V) and Latch-up Immunity (+/-200 mA).
Technical Specifications
Foundry, Node
GSMC 0.13um
Maturity
Silicon proven
Related IPs
- VeriSilicon SMIC 0.13um Syn. LP DROM Compiler, Memory Array Range:128 to 1Mega Bits
- VeriSilicon SMIC 0.13um Syn. LP VROM Compiler, Memory Array Range:128 to 1Mega Bits
- GSMC 0.13um Low Power Process Delay Cells
- GSMC 0.13um 1.5v APLL
- GSMC 0.13um Low Power e-Flash 1.5V POR
- GSMC 0.13um 5v-3.3v&1.5v Power Regulator