Globalfoundries 22nm MIPI D-PHY Tx only V1.1@1.5GHz

Overview

The 2nd Generation MIPI D-PHY v1.1 Tx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. The D-PHY IP is available on both GF’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process technologies. GF 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing, digital TVs, set-top boxes, smartphones and consumer products in terms of its power, performance and area (PPA) optimization, while its 22nm ultra-low leakage (22ULL) technology provides significant power reduction to support IoT and wearable device applications, where power is of paramount importance. MIPI D’Phy as a physical serial communicating layer is gaining traction in the today’s power hungry mobile and mobile related applications due to its low power consumption operation.

The D-PHY IP is also available as a Rx only IP for companies looking to save silicon area and further improve power consumption. The MIPI D-PHY IP is seamlessly integrated with Arasan’s own DSI Tx and DSI Rx IP Cores as part of its Total MIPI Display IP Solution for wearables and IoT.

The MIPI D-PHY IP is also available off the shelf on the GF 40nm, 28nm, 16nm and 12nm process technologies. A D-PHY / C-PHY Combo HDK based on Arasan’s ASIC applications on GF 28nm process is also available to licensees of Arasan’s DPHY IP or CPHY IP to prototype their Display or Imaging products before going to production. Customers can license with confidence in Arasan’s MIPI D-PHY IP knowing they can prototype with the real silicon on GF 22nm process, which is used in a MIPI Compliance Tester to test for MIPI CSI, DSI, D-PHY and C-PHY Standards Compliance. We are Compliance!

Key Features

  • Compliant with MIPI D-PHY v1.1 specifications
  • Supports MIPI DSI and MIPI CSI-2 interfacing up to 10 Gb/s
  • Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
  • Silicon proven in TSMC 22nm process
  • Asynchronous transfer at low-power mode with a bit rate of 10 Mb/s
  • Ultra low-power mode, and high-speed mode for clock lane
  • Ultra low-power mode, high-speed mode, and escape mode for data lane
  • Compliant to the MIPI D-PHY spec v1.2
  • Support HiSPi-SLVS TX compatible mode
  • Supports 1, 2 or 4 MIPI D-PHY data lanes
  • Supports non-burst mode with sync events for transmission of DSI packets only
  • Supports LP (low power) mode during vertical and horizontal blanking
  • On-chip differential 100? terminations with calibration
  • Support for DPHY Ultra Low Power State
  • Built-in self test function
  • PHY-Protocol Interface (PPI) for connection to DSI and CSI-2 protocol layers
  • Support wire-bond and flip-chip package type

Benefits

  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Process & Foundry
    • Available in various foundry processes
    • No external (off-chip) components required
    • Can be ported to other processes
  • Silicon proven
  • Extensive Quality Methodology

Deliverables

  • GDS-II Database
  • LVS Netlist
  • Physical Abstract Models (LEF)
  • Timing Models (LIB)
  • Process Specific Integration Guide

Technical Specifications

Maturity
Silicon Proven
Availability
Now
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Semiconductor IP