IP Catalog > Memory Controller/PHY IP > GDDR IP > GDDR7 PHY & Controller

GDDR7 PHY & Controller

Overview

The GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each byte consists of ten DQ signals and one DQE signal, while the GDDR7 also supports NRZ I/O signaling for low-power operation. With a maximum speed of 32 Gbps per pin, The GDDR7 PHY delivers a peak bandwidth of up to 128 GB/s per memory device. Designed for advanced FinFET process nodes, this PHY is optimized for seamless integration into cutting-edge applications.

The comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.

Key Features

  • GDDR7 with data rate up to 32Gbps
  • Driver strength and ODT auto calibration
  • Auto Hardware/Software CA Bus Training, ERR Training, Read/Write Training with FIFO/LFSR mode
  • Auto 2D read VREF Training
  • Supports Burst length: 16 Symbols (PAM3) or 32 Symbols (NRZ)
  • Supports read/write CRC
  • Programmable READ and WRITE latency
  • Rx DFE for data inputs, with receiver characteristics programmable per pin
  • 3 frequency points auto-change
  • Supports PHY low power mode with GDDR7 SGRAM in self-refresh sleep mode/hibernate self-refresh sleep mode
  • Configurable 4-channel/2-channel mode
  • At-Speed BIST loopback, At-Speed/Stuck-At Scan, boundary scan
  • Internal high-performance low-jitter PLL
  • Per-bit Tx and Rx data phase delay and Vref adjustment
  • Tx de-emphasis EQ and Rx DFE EQ to improve signal integrity
  • Accommodates Voltage/Temperature timing drift
  • 1.35V ±0.0405V or 1.2V ±0.036V supply for I/O interface (VDDQ)
  • Pseudo open drain (POD-135 and POD-12) compatible outputs
  • Dynamic Read/Write Training with auto-refresh synchronization function
  • Dynamic command address timing adjustment using CAOSC
  • Optional package/PCB design and SI/PI analysis service
  • Supports Micron, Samsung, Hynix memory devices

Benefits

  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Extensive EDA tool support for various design and automation flow
  • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
  • Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing

Block Diagram

GDDR7 PHY & Controller Block Diagram

Deliverables

  • Extensive documentation
  • Models
  • LIB
  • LEF
  • Place-and-route abstracts
  • LVS netlist
  • GDSII files

Technical Specifications

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