GDDR6 Assertion IP

Overview

Key Features

• Specification Compliance
• Compliant to ARM GDDR6 protocol
• Supports GDDR6 memory devices from all leading vendors.
• Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
• Supports all the GDDR6 commands as per the specs.
• Supports 2 separate independent channels with point-to-point interface for data, address and command.
• Supports Double Data Rate (DDR) or Quad Data Rate (QDR) data.
• Supports Pseudo channel mode operation.
• Supports up to 32GB device density.
• Supports X8 and X16 Mode.
• Supports Bank grouping and 16 internal banks per channel.
• Supports Data bus inversion (DBI) & Command Address bus inversion (CABI).
• Supports Read/Write data transmission integrity secured by cyclic redundancy check.
• Supports READ/WRITE EDC on/off mode.
• Supports Programmable EDC hold pattern for CDR.
• Supports Low Power modes.
• Supports Refresh Management (RFM).
• Supports Auto refresh & self-refresh modes.
• Supports On-die termination operation.
• Supports Vendor ID1 and ID2 for identification.
• Supports COMMAND ADDRESS, WCK2CK,READ/WRITE Training mode’s.
• Supports IEEE.1149.1 boundary scan operation.
• Supports programmable clock frequency of operation.
• Checks for following
• Check-points include power on, Initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports all mode registers programming.
• Supports for power down features.
• Supports for input clock stop and frequency change.
• Quickly validates the implementation of the standard GDDR6 protocol JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
• Bus-accurate timing for min, max and typical values.
• Constantly monitors GDDR6 behavior during simulation.
• Protocol checker fully compliant with GDDR6 standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Master mode, Slave mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV GDDR6 VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure GDDR6 Assertion IP functionality.

Benefits

• Runs in every major formal and simulation environment.

Block Diagram



Deliverables

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.

Technical Specifications