The GDDR7 Verification IP provides an effective & efficient way to verify the components interfacing with GDDR7 interface of an ASIC/FPGA or SoC. The GDDR7 VIP is fully compliant with Standard GDDR7 specification from JEDEC. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
GDDR 7 Verification IP
Overview
Key Features
- Compliant to JEDEC JESD239A GDDR7 Specification.
- Supports connection to any GDDR7 Memory Controller IP communicating with a JEDEC compliant GDDR7 Memory Model.
- Available in all memory sizes from upto 64Gb.
- Command Supported
- Write: Write, Write Auto-Precharge
- Read: Read, Read Auto-Precharges
- Mode Register Set, Activate, Load FIFO
- Precharge: PREab, PREb
- Refresh: REFab, REFpb
- Refresh Management: RFMab, RFMpb
- Power Down Entry (PDE), Power Down Exit (PDX)
- Self-Refresh Entry (SRE), Self-Refresh Exit (SRX)
- Sleep Entry, Self-Refresh Sleep Entry
- Training Commands
- Reports various timing errors, which can be used to check any timing violations
- Supports command address bus inversion(CABI) and command address parity(CAPAR) functionalities
- Supports Cyclic Redundancy Check (CRC) on write and read data
- Supports ECC engine test mode of operation
- Provides full control to the user to enable/disable various types of messages.
- Supports full-timing models or bus functional models.
- Supports advanced SystemVerilog features like constrained random testing.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of various Regression Test Suites.
- 24X5 customer support.
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide complete solution and easy integration in IP and SoC environment.
Block Diagram
Deliverables
- GDDR7 Monitor & Scoreboard
- GDDR7 Memory Controller BFM/Agent
- GDDR7 PHY BFM model
- GDDR7 Phy Monitor and Scoreboard
- Test-Bench Configurations
- Test Suite (Available in Source code)
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes