IP Catalog > Interface IP > Interconnect IP > Ethernet IP > Ethernet PHY IP > GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP

Overview

An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX operation is known as an Ethernet PHY. The EPHY links to the Media Access Control Layer (MAC) through the Giga Media Independent Interface (GMII), and on the media side, it offers a direct interface to either UTP5/UTP3 cable for 10BASE-Te Ethernet or Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet. The CMOS technology used by the Ethernet PHY has low power and great performance. The Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), and Twisted Pair Physical Medium Dependent Sub-layer are all included, as per the 100BASE-TX physical layer functionality as specified by IEEE802.3u (TP-PMD, 100BASE-TX only). Additionally, the EPHY has a powerful auto-negotiation feature that uses automated media speed/duplex and protocol selection matching.

Key Features

  • Fully compliant with the IEEE 802.3 / 802.3u10BASE-Te, 100BASE-TX
  • Interface available to Compliant with TP-PMD standard: ANSI X3.263-1995
  • Compliant with FDDI-PMD standard: ISO/IEC 9314-3: 1990 and ANSI X3.166-1990
  • Support GMII interface to the MAC controller.
  • Serial management interface compliant with IEEE 802.3u (MDIO)
  • Support Full-Duplex or Half-Duplex Operation
  • Support Auto-Negotiation Next Page /Parallel Detection function
  • Compliant with IEEE 802.3u, and Manual configuration is also supported.
  • Automatic Polarity Correction
  • Support auto MDI/MDIX crossover function for 10BASE-Te / 100BASE-TX
  • High performance baseline wander correction (BLW) Circuit
  • High Performance Digital Clock recovery algorithm
  • High performance Digital Equalizer for ISI mitigation
  • LED Driver for Link, Activity, Duplex, Collision, and Speed Status
  • Low Power design, with support 803.2az standard-2010 (EEE)
  • Support MAX 300ppm sampling offset
  • Silicon Proven in UMC 40nm LP

Block Diagram

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP Block Diagram

Deliverables

  • Detailed Datasheet
  • Verilog behaviour model (A) for simulation
  • Liberty (db./.lib) for synthesis, STA, and equivalence checking
  • CTL / CTLDB for DFT
  • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
  • LEF for APR
  • CDL for LVS connection

Technical Specifications

Foundry, Node
UMC 40LP
Maturity
In Production
Availability
Immediate
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