GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+

Overview

For Gigabit 10/100/1000 Ethernet applications, the GPHY is a highly integrated single chip. It is a singleport, IEEE 802.3u/ab compatible, power efficient Giga Ethernet physical layer transceiver. It can operate in 10BASE Te, 100BASE-TX, and 1000BASE-T modes. This GPHY uses either RGMII or GMII to connect to the Media Access Control Layer (MAC). It could support UTP5/UTP3 cable for 10BASE-Te Ethernet or Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet and 1000BASE-T Giga Ethernet. It includes the Physical Coding Sublayer (PCS), Physical Medium Attachment Layer (PMA), and Twisted Pair Physical Medium Dependent Sub-layer (TP-PMD, 100BASE-TX only) as well as all of the physical layer functionality for 1000BASE-T as described by IEEE 802.3ab and 100BASE-TX, respectively. Additionally, this GPHY has a strong automated negotiation feature, automatic media speed- duplex selection, and protocol selection.

Key Features

  • IEEE 802.3-2008, IEEE 802.3az fully standards compliant
  • IEEE 1588-2008 support
  • BroadR-Reach™ support
  • Dual port MAC interface: GMII (10/100/1000BASE-T), MII (10/100BASE-T).
  • Auto-negotiation support
  • Automatic detection and correction of pair swaps (Auto-MDIX), pair skew and pair polarity
  • 6 different operating modes: 1000BASE-T Full Duplex and Half Duplex, 100BASE-TX Full Duplex and Half Duplex, 10BASE-T Full Duplex and Half Duplex
  • Management interface
  • Baseline wander compensation
  • On-chip transmit wave-shaping
  • On-chip hybrid circuit
  • 10KB jumbo frames
  • Internal, external and remote loop back
  • Hardware configuration for default operation
  • Power down mode, interrupt support
  • IEEE 1500 support for SoC testing integration
  • LED indication: link mode, status, speed, activity, and collision
  • Silicon Proven in TSMC 28nm HPC+

Block Diagram

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+  Block Diagram

Deliverables

  • Detailed Datasheet
  • Verilog behaviour model (A) for simulation
  • Liberty (db./.lib) for synthesis, STA, and equivalence checking
  • CTL / CTLDB for DFT
  • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
  • LEF for APR
  • CDL for LVS connection

Technical Specifications

Maturity
In Production
Availability
Immediate
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Semiconductor IP