Fully-integrated top-metal mesh sensor protecting integrated circuits against tampering attacks

Overview

Key Features

• fully integrated countermeasure against cut and strap attacks
• dynamic detection of tampering attempts
• shield characteristics adjustable through a graphical user interface: security level; mesh number and density; gate number; power consumption;via distribution; routing congestion
• easy integration in typical design flows through RTL files and back-end scripts
• fully compatible with both Cadence SoC Encounter and Synopsys IC Compiler
• silicon proven in 110 nm, 90 nm, 65 nm and 55 nm CMOS processes
• typical power consumption: 5 µW to protect a 2 mm² area in a 65 nm CMOS process
• typical silicon area overhead lower than 3%
• straightforward integration through AMBA APB bus (customized on request)

Benefits

• Tamper-resistant
• Dynamic detection
• Configurable architecture
• Adjustable parameters
• Silicon proven

Deliverables

• VHDL source codes
• VHDL testbenches
• Synopsys synthesis scripts
• back-end software tool
• design specification
• integration manual

Technical Specifications