FPGA Dual HDLC Serial Port
Overview
The Dual HDLC controller provides two full-duplex HDLC channels, each with 512-byte data FIFO buffers for both directions. Recognizing that in most applications the various HDLC options rarely change, the design uses pins to control these options rather than dedicated control registers. This essentially eliminates initialization requirements.
Key Features
- General Features:
- Optimized for an Actel A3P060 in a 100-pin VQFP package.
- Also suitable for embedding in an A2F060 or larger.
- 512 byte FIFO buffers for both receive and transmit in each channel, using the FPGA memories.
- 8-bit bus interface.
- 8-bit Baud Rate Generator in each channel.
- Serial clock is independent between channels.
- HDLC Features:
- Automatic Flag generation and checking.
- Automatic zero-insertion and deletion.
- Automatic 16-bit CRC generation and checking.
- Optional 16-bit frame preamble.
- Idle line of Flags or Always High.
- Optional 8-bit address compare, with two address registers per channel.
- DPLL for clock recovery (runs at 16x or 32x data rate).
- Data encode/decode: NRZ, NRZI, Biphase-Level, Biphase-Mark or Biphase-Space.
Technical Specifications
Availability
now
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