FPD VIP

Overview

FPD Verification IP is fully compliant with Standard FPD Link I, II and III. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively

FPD VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

FPD VIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports full FPD Source and FPD device functionality.
Supports 8 serial data lines (A0 through A7) and two clock lines (CLK1 and CLK2) in the FPD interface.
Supports DDC2B protocol to retrieve the EDID data structure from display.
Supports High-Bandwidth Digital Content Protection (HDCP) v1.3
Supports EDID 1.3 and 2.0 data structures in FPD source and FPD devices.
Supports DC balanced and unbalanced modes of operation.
Supports following RGB Pixel formats in DC balanced and unbalanced mode of operation,
- 18-bit single pixel
- 24-bit single pixel
- 18-bit dual pixel
- 24-bit dual pixel
Supports Intra-pair and Inter-pair Skew insertion and detection
Supports the following common display resolutions,
- 640 x 480
- 800 x 600
- 1024 x 768
- 1280 x 1024
- 1600 x 1024
- 1600 x 1200
- 1920 x 1080
- 1900 x 1200
- 2048 x 1536
Supports user controlled Default Configurations of video formats for a FPD source and FPD devices.
The model has a rich set of configuration parameters to control FPD functionality.
Callbacks in FPD source and Device for user processing of data.
Status counters for various events in bus.
The source is capable of inserting various transmit errors.
Supports constraint randomization
The FPD device is capable of detecting various errors.
Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
FPD Verification IP comes with complete test suite to verify each and every feature of FPD Link I, II and III.
Functional coverage for complete features.

Benefits

Faster test bench development and more complete verification of FPD designs.
Easy to use command interface simplifies test bench control and configuration of FPD source and device.
Simplifies results analysis.
Runs in every major simulation environment

Block Diagram

Deliverables

Complete regression suite containing all the FPD testcases.
Examples showing how to connect various components, and usage of FPD source,device and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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