FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)

Overview

Now available up to 150Mhz (90Mhz previously)

V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).
At a maximum pixel rate of 90Mhz, LVDS data line speed is 630Mbps, providing a total maximum bandwidth of 3.15Gb/s (394Mbytes per second).

Key Features

1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
3.3V/1.8V 10% supply voltage, 0/+125C
Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
Up to 3.15Gbps bandwidth (8 to 90Mhz pixel clock for 1 channel)
Parallel output clock edge is programmable
Spread-spectrum input clock support
Compact core cell area : [contact us]
Built-in power pads with ESD protection.
Low leakage power-down mode <0.1uA.
Equivalent part : Thine’s THC63LVD104A

Benefits

Very compact design
customization for your own project
reliability

Deliverables

Design kit includes :

LEF view and abstract gdsII
Verilog HDL behavioral model
Liberty (.lib) timing constraints for typical, worse and best corner case
Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Technical Specifications

Maturity

pre-silicon

Availability

now

SMIC

Pre-Silicon: 180nm G

Silterra

Pre-Silicon: 180nm

TSMC