Floating point adder
Overview
Floating point adder
Key Features
- Combinational circuit
- The precision format is parameterizable for either IEEE single, double precision, or a user-defined custom format
- Exponents can range from 3 to 31 bits
- Fractional part of the floating-point number can range from 2 to 253 bits
- Better timing and area
Benefits
- Compliant with IEEE standard 754-2008
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Maturity
Pre Silicon
Availability
Yes
Related IPs
- Single precision, IEEE 754, floating point adder
- IEEE 754 Floating Point Coprocessor
- Floating Point Megafunctions
- Floating Point Processor for Embedded Systems
- Low power 32-bit processor supporting single precision floating point in hardware
- Library of mathematical and floating point (FP) components