FlexRay Verification IP

Overview

FlexRay Verification IP provides an smart way to verify the FlexRay component of a SOC or a ASIC. The SmartDV's FlexRay Verification IP is fully compliant with standard FlexRay 3.0.1 (plus addendum) Specification and supports all the frame types such as Static and Dynamic frames.Also supports all operating modes such as STANDBY,NOCE,STARTUPFRAMECAS,STARTUPFRAME and SINGLESLOT modes.

Flexray 3.0.1 Verification IP includes an extensive test suite covering most of the possible scenarios. It can perform all protocal tests and moreover it allows an easy generation of very high number of patterns and a set of specified patterns to stress the DUT.

FlexRay Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

FlexRay Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Fully compatible with FlexRay specification version 3.0.1.
Support Full Duplex of operations.
Complete FlexRay Tx/Rx functionality.
Supports cluster wakeup and startup.
Transmit and receive commands allow the user to transmit and receive FlexRay data.
Operates as a Tx or as a Rx.
Supports 2.5, 5 and 10 Mbit/s bitrate.
Support Bit alignment
All types of frame generation.

Static frames
Dynamic frames

Various kinds of Tx and Rx errors insertion and detection.
Syntax errors

Frame ID error (Frame ID = 0)
Header CRC error
CRC error
Over and undersize errors

Content errors

Cycle Count error
Frame ID error
Startup, Sync & Null frame errors w.r.t Dynamic segment
Startup & Sync frame errors w.r.t Static segment
Reception of Null frame
Aborting in middle of transaction

Configurable receive FIFO depth
Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Supports constraints randomization.
Supports glitch insertion and detection.
Status counters for various events on bus.
Callbacks in Tx,Rx and monitor for various events.
FlexRay Verification IP comes with complete testsuite to test every feature of FlexRay specification.
Functional coverage for complete FlexRay features.

Benefits

Faster testbench development and more complete verification of FlexRay designs.
Easy to use command interface simplifies testbench control and configuration of TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the FlexRay testcases.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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