FlexRay Synthesizable Transactor provides a smart way to verify the FlexRay component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's FlexRay SynthesizableVIP is fully compliant with standard FlexRay Specification and provides the following features.
FlexRay Synthesizable Transactor
Overview
Key Features
- Fully compatible with FlexRay specification Version 3.0.1
- Supports complete FlexRay Tx/Rx functionality
- Supports full Duplex of operations
- Operates as a Tx or as a Rx
- Supports 2.5, 5 and 10 Mbit/s bitrate
- Supports all types of frame generation
- Static frames
- Dynamic frames
- Supports transmit and receive commands that allow the user to transmit and receive FlexRay data
- Supports cluster wakeup and startup
- Supports Various kind of Tx and Rx errors insertion and detection
- Syntax errors
- Frame ID error (Frame ID = 0)
- Header CRC error
- CRC error
- Over and undersize errors
- Content errors
- Cycle Count error
- Frame ID error
- Startup, Sync & Null frame errors w.r.t Dynamic segment
- Startup & Sync frame errors w.r.t Static segment
- Reception of Null frame
- Supports configurable receive FIFO depth
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the FLEXRAY testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes