Flexible Deterministic Ethernet IP Core with TSN (Time Sensitive Networking)

Overview

TTTech Industrial’s Flex IP Core is a flexible design IP for customized chip or ASIC products. Flex IP Core offers a wide range of configurable features and a verification environment that enables developers to check the coverage and quality of IP. Flex IP Core source code is developed and delivered according to ASIC requirements e.g. memories instantiated on top-level.

Key Features

Ports

3 to 12 ports; 10/100/1000 Mbit/s

Physical Interfaces

MII, GMII, RMII, RGMII, SGMII,
100BASE-FX, 1000BASE-X
PPS (Pulse-Per-Second) output
Avalon slave interface for management register access

IEEE 802.1AS Time Synchronization
IEEE 802.1Qbv Scheduled Traffic
IEEE 802.1Qcc SRP Enhancements
IEEE 802.1Qbu Frame Preemption
IEEE 802.1CB Frame Replication and Elimination
IEEE 802.1Qci Filtering and Policing (Available 2020)

IEEE 802.1AS Time Synchronization for Time-Sensitive Applications (gPTP)
IEEE 802.1Qav Forwarding and Queuing for Time-Sensitive Streams (FQTSS)

HSR RedBox, HSR End Node and QuadBox support

PRP RedBox and DANP support

IEEE 802.1Q

Port-based VLANs and VLAN tagging
Prioritization of packets on egress ports
Untagging of VLAN frames on egress ports

Clock Synchronization

IEEE 802.1AS (including multi-time domain support)
IEEE 1588-2008 layer 2 one/two-step end-to-end transparent clock support

Switching Engine

Store and forward architecture providing full cross-sectional bandwidth
128 Kbit frame buffer per port
4096 VLANs
16 MAC address filters per port
Up to 4096 entry MAC address hash-based learning table
Up to 4096 policer per port
8 traffic shapers per port (optional)
Static configuration of MAC addresses
Flow identification-based MAC addresses
Ingress rate-limiting on a per-port basis for unicast, multicast, and broadcast traffic
Embedded Software Linux kernel module
Native Linux interfaces / user space configuration library
Edge PTP in binary format for ARM – for IEEE 1588 / IEEE 802.1AS clock synchronization
MSTP including additions for engineered traffic (802.1Qcc)
Open source support for SNMP and NETCONF

Benefits

Configurable and scalable features for optimal silicon design-in
Delivered according to ASIC development requirements
Provides guaranteed low-latency communication for critical traffic
Includes the latest IEEE 802.1 Ethernet standards

Deliverables

IP core design files in source code
Software and device drivers for Linux
YOCTO based build system
Integration manual
Verification environment
Test report
Technical documentation

Technical Specifications

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