FIFO Memory Interface to the 10/100 Mbps Ethernet MAC
Overview
The M-MIIFIF(TM) module from Mentor Graphics is a flexible FIFO module with transmit and receive buffering that can significantly improve the performance of embedded 10/100 Mbps Ethernet systems. It integrates with the PE-MACMII (TM)10/100 Mbps Ethernet MAC module (also available from the Mentor Graphics Ethernet IPlibrary) and functions in all of the PE-MACMII’ smodes.
Key Features
- Operates at 10- or 100-Mbps
- � Provides data queuing for increased system level throughput
- � User definable storage sizes
- � Clock frequency independent I/O ports
- Single or multiple word data transfers
- Programmable Rx and Tx storage level indicators, plus Tx storage under-run indication
- CPU frame insertion and inspection
- Automatic pause frame handshaking
- Programmable pause frame handshaking reassertion interval
- Graceful Rx memory full frame drop
- Graceful enable and disable
- Programmable frame or word cut-through threshold
- Tx storage frame rewind capabilities
- Full memory utilization
- Optional per transmit frame MAC configuration data supported
- Low gate count
- Fully synthesizable
- Scan, insertion-friendly design
- Uses synchronous dual-port memories
Deliverables
- Verilog RTLsource code
- Functional testbench
- Synopsys constraint files
- Module-level documentation
Technical Specifications
Related IPs
- I2C Controller IP – Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses or direct to/from Registers or Memory
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- 10/100 Mbps Dual-Speed Ethernet MAC
- Ethernet 10/100 MAC
- 10/100/1000 Mbps Ethernet MAC
- Low-Latency 10/100/1000 Ethernet MAC