Extremely Low Latency Matching Engine Synthesizable IP Core

Overview

Axonerve is a next generation variant of the content-addressable memory (CAM) solution. Its unique algorithmic matching engine realizes high-speed & low-latency content matching at ultra-low power consumption.
Axonerve can perform continuous search operation with extremely low latency and achieve 150MSPS to track 100Gbps network packets. It can support exact and wildcard matching for N-tuple header fields. It also provides a priority function that determines which one should be finally selected out of multiple matches. You don’t need to sort or update a whole entry table any more to change the matching order.
Axonerve is a fully-synthesizable IP core. It adopts common 6T-SRAM technology and requires no special memory structure design. It leads to power and area saving, and enables you to implement single or multiple instances of Axonerve IP cores in FPGA as well as ASIC.

Key Features

  • Key length
    • 144/288/576/1152 bits
  • Entry capacity
    • 1M entries / 288[bit] (*)
  • Search latency
    • 10 cycles (on-chip memory mode)
    • TBD cycles (off-chip memory model)
  • Search speed
    • 150MSPS @150MHz
  • Operations
    • Entry write/read/delete/update
    • Aging operations (optional)
  • OpenFlow friendly
    • Field masking for N-tuple header field
    • Priority setting for every entry
  • 28nm process silicon proven

Block Diagram

Extremely Low Latency Matching Engine Synthesizable IP Core Block Diagram

Applications

  • SDN/OpenFlow switch
  • L2 MAC lookup
  • Deep packet inspection
  • Carrier grade NAT
  • Memcached server
  • Dedup storage
  • Virus signature matching
  • IoT data mining
  • Key-value Store (KVS)

Technical Specifications

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Semiconductor IP