External Memory Interface (EMIF)

Overview

EMIF provides an smart way to verify the EMIF component of a SOC or a ASIC. The SmartDV's EMIF is fully compliant with standard EMIF Specification and provides the following features.

External Memory Interface (EMIF) is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

External Memory Interface (EMIF) comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports 100% of EMIF standard protocol.
Supports all the EMIF commands as per the specs.
Supports following external devices.
- Pipelined synchronous burst SRAM (SBSRAM).
- Synchronous DRAM (SDRAM).
- Asynchronous devices, including SRAM, ROM and FIFO’s.
- An external shared-memory device.
Supports external memory power-down, sleep and wakeup modes.
Supports all external memory speeds.
Supports programmable write cycle length and read cycle length.
Supports extended wait.
Supports neither page/burst mode read for NOR flash.
Supports data bus parking.
Supports select strobe mode.
Supports interrupt.
Supports ECC.
Supports all mode register programming.
Checks for following
- Power on, Initialization and Power off rules.
- State based rules, Active Command rules.
- Read/Write Command rules.
- All timing violations.
Supports callbacks for user to get command data on bus and user to access the data observed by monitor.
Protocol checker fully compliant with EMIF specification.
Constantly monitors EMIF behavior during simulation.
Quickly validates the implementation of the EMIF standard specification.
Bus-accurate timing for min, max and typical values.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Status counters for various events on bus.
EMIF comes with complete testsuite to test every feature of EMIF standard specification.

Benefits

Faster testbench development and more complete verification of EMIF designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the EMIF testcases.
Complete UVM/OVM sequence library for EMIF controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all classes, tasks and functions used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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