Flash memory forms a basic constituent in many FPGA based embedded systems using Xilinx SRAM based FPGAs. This is primarily because they store the bitstream file for the FPGA using which the FPGA configures itself at every startup. After configuration, the flash memory is available for user data storage and can be used for non-volatile data storage as long as it is outside of the bitstream area.
External Flash Memory Interface IP
Overview
Key Features
- AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
- Page-wise programming according to the flash memory requirements handled by the IP
- Memory single bit error detection and correction implemented in the IP-core.
- User configurable, industry standard NOR flash memories can be interfaced with the IP on SPI and Quad-SPI interfaces.
Benefits
- The external flash memory interface IP designed at Faststream technologies allows accessing these memory locations as a memory mapped interface and makes the controller agnostic of the underlying SPI interface on which the memory is being interfaced.
Block Diagram
Applications
- Flash Memory
Deliverables
- System Matlab model
- Synthesizable Verilog RTL
- Test Benches for verification
- Documentation
Technical Specifications
Related IPs
- SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface
- External Memory Interface (EMIF)
- SPI (Serial Peripheral Interface) Flash Verification IP
- External SRAM and Flash Memory Controller
- I2C Controller IP – Slave, User Register Interface, No CPU Required
- I2C Controller IP – Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses or direct to/from Registers or Memory