eUSB 2.0 PHY - TSMC N5 x1, North/South (vertical) poly orientation

Overview

The vendor provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0 specifications. The eUSB2 PHY IP has industry's best combination of low area and low power in leading process technologies from 7nm and below.

The eUSB2 IP is built on years of customer successes with the vendor’s silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm.

With over 3,000 design wins and over 4 billion silicon-proven units shipped, the vendor’s USB IP solution, consisting of digital controllers, PHYs, IP subsystems, and verification IP, enables designers to lower integration risk and speed time-to-market.

Key Features

  • Designed for 7nm processes and below
  • Supports the USB 2.0 protocol and High Speed, Full Speed, and Low Speed data rates
  • eUSB2 PHYs supports USB 2.0, 3.0, 3.1 and 3.2 Device, Host and Dual Role configurations

Block Diagram

eUSB 2.0 PHY - TSMC N5 x1, North/South (vertical) poly orientation Block Diagram

Technical Specifications

Foundry, Node
TSMC N5 x1, North/South (vertical) poly orientation
TSMC
Pre-Silicon: 5nm
×
Semiconductor IP