Ethernet TSN Switch IP Core - Efficient and Massively Customizable

Overview

Key Features

• Full wire-speed on all ports for all Ethernet frame sizes.
• Store and Forward shared memory architecture.
• Support for Jumbo frame packets of any size limited only by the available packet buffer memory.
• Passes maximum overlap mesh test (RFC2899) using all ports for all packet sizes up to 1518 bytes.
• Time-Sensitive Networking:
  • IEEE Std 802.1Qci-2017: Per-Stream Filtering and Policing
  • IEEE Std 802.1CB-2017: Frame Replication and Elimination for Reliability
  • IEEE Std 802.1Qbv-2015: Enhancements for Scheduled Traffic
  • IEEE Std 802.1Qav-2009: Credit Based Shaper
• Queue management operations:
  • Disable scheduling of packets on a port.
  • Disable queuing new packets to a port.
  • Allow a port to be drained without sending out packets.
  • Allow checking if a port is empty or not.
• Input and output mirroring.
• RSPAN - Remote Switch Port Analyzer
• 4 source MAC address ranges with a number of different actions.
• 4 destination MAC address ranges with a number of different actions.
• 1,024 entry L2 MAC table, hash based 4-way.
• 4,096 entry VLAN table.
• 16 entry synthesized CAM to solve hash collisions.
• 4 entries of the synthesized CAM are fully maskable.
• 64 entry L2 multicast table.
• Automatic aging and wire-speed learning of L2 addresses. Does not require any CPU/software intervention.
• Spanning tree support, ingress and egress checks.
• 16 multiple spanning trees, ingress and egress checks.
• Egress VLAN translation table allowing unique VID-to-VID translation per egress port.
• VLAN priority tag can bypass VLAN processing and be popped on egress.
• 496 entries of ingress classification / ACL Lookups. The classification / ACL keys are configurable for each source port and the fields are selected from a incoming packets L2, L3 or L4 fields. The selection is described in 10.2 The classificaiton / ACL key can be up to 372 bits long. The classification / ACL lookup is based on a combination of hash and TCAM. The actions which can be done is listed below:
  • Multiple actions can be assigned to each result. All results can be done in parallel if the user so wishes.
  • Result action can be to drop a packet.
  • Result action can be to send a packet to the CPU port.
  • Result action can be to send a packet to a specific port.
  • Result action can be to update a counter. There are 32 counters which can be used by the classification / ACL engine.
  • Result action can be to force packet to a specific queue on a egress port.
  • Result action can be to assign a meter/market/policer to measure the packet bandwidth.
  • Result action can be to assign a color to the packet which is used by the meter/marker/policer.
  • Result action can be to force the packet to use a specific VID when doing the VLAN table lookup.
  • Result action can be to do a input mirror on a packet.
  • Result action can be to not allow the packet to be learned in L2 MAC table.
• The ingress configurable classification / ACL engine can use the type and code fields from ICMP frames.
• The ingress configurable classification / ACL engine can use the fields, including the group address, from IGMP frames.
• 1843200 bits shared packet buffer memory for all ports divided into 1536 cells each of 150 bytes size
• 8 priority queues per egress port.
• Configurable mapping of egress queue from IP TOS, MPLS exp/tc or VLAN PCP bits.
• 32 ingress admission control entries.
• Deficit Weighted Round Robin Scheduler.
• Bandwidth shapers per port.
• Individual bandwidth shapers for each priority on each port.
• Individual bandwidth shapers for each queue on each port.
• Egress queue resource limiter with four sets of configurations.
• Configuration interface for accessing configuration and status registers/tables.
• Multicast/Broadcast storm control with separate token buckets for flooding, broadcast and multicast packets.
• Multicast/Broadcast storm control is either packet or byte-based, configurable per egress port.
• LLDP frames can optionally be sent to the CPU.
• Attack prevention by TCP flag rules combined with TCP-port and IP address checks, this also includes IMCP length attack checks

Benefits

• Quick customization thanks to a massively parametrized design, and the unique FlexSwitch tool-chain
• Port speeds from 10 Mbit/s to 400 Gbit/s. Mixed port speeds are supported.
• Number of ports from 4 to 128 with optimized design for each configuration.
• All table sizes can be configured such as L2 hash tables, VLAN tables, L3 LPM and direct host tables, classification tables etc.
• Most features can selectively be added or removed and the design will be automatically optimized for the chosen feature set.
• Design, datasheet and YAML files are automatically created based on the chosen parameter set.
• Delivered as non-encrypted, human readable, verilog source code

Block Diagram

Applications

• Industrial
• Automotive
• Aviation
• Space

Deliverables

• IP core delivered as non-encrypted Verilog source code.
• Datasheet with theory of operations and automatically created register description.
• Easy to parse YAML file for register mapping.
• Verilog testbench for checking simulator compliance and as an example of driving the cores interfaces.
• Low-level device driver

Technical Specifications