1G Ethernet Switch IP Core

Overview

Ultra compact Ethernet Switch designed for easy use, targets applications requiring low size and a versatile solution

The 1G Ethernet Switch IP is a switching core that is a highly configurable and size-optimized implementation of a non-blocking crossbar switch that allows continuous transfers between up to 16 ports Ethernet ports via 1 Gbps GMII interfaces.

The 1G Ethernet switching IP supports MAC learning and implements a store-and-forward switching approach to fulfill Ethernet standard policy regarding frame integrity checking.

The 1G Ethernet switching IP supports up to 16 ports, where each port provides GMII native interface for Ethernet PHY devices. The number of ports 2-16 is configurable at compile time. Comcores 1G Ethernet Switch IP core is a silicon agnostic implementation targeting both ASICs and FPGAs.

Key Features

  • Delivers Performance
    • Up to 16 ports configurable at compile time
    • Configurable queuing behavior (round-robin, fair queuing)
    • Supports Ethernet Multicast
    • Ultra compact size
  • Feature Rich
    • Automatic MAC addresses learning and aging
    • Support programmable static forwarding entries
    • Full duplex Ethernet interfaces
    • Support VLAN
    • AXI4-Lite
  • Easy to use
    • GMII interfaces for attaching to an external Physical Layer device (PHY)
    • Can be used in managed or unmanaged implementations
  • Silicon Agnostic
    • Designed in VHDL and targeting both ASICs and FPGAs

Block Diagram

1G Ethernet Switch IP Core Block Diagram

Deliverables

  • The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
    • Solid documentation, including User Manual and Release Note
    • Simulation Environment, including Simple Testbed, Test case, Test Script
    • Access to support system and direct support from Comcores Engineers
    • Synopsys Lint and CDC

Technical Specifications

Maturity
Mature
Availability
Avaliable
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Semiconductor IP