eCPRI Verification IP

Overview

The SmartDV's eCPRI Verification IP is fully compliant with eCPRI Specification V2.0 and verifies eCPRI interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

eCPRI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

eCPRI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with eCPRI Specification V2.0.
Complete eCPRI Tx/Rx functionality.
Supports the eCPRI layer of the eCPRI specification.
Supports 5G and enables increased efficiency.
Supports Ethernet 10G/25G/40G/100G Ethernet Speeds
Supports the following message types.

IQ Data
Bit sequence
Real time control data
Generic data transfer
Remote memory access
One way Delay Measurement
Remote reset
Event Indication
IWF start-up
IWF operation
IWF mapping
IWF delay control
Vendor Specific

Supports Control and Management data transfer.
Supports data transfer through Ethernet/UDP/IP Interfaces.
Full support for IEEE 1588-2008 and IEEE 1588-2019
Supports delay management.
Supports 8B/10B line coding
Supports insertion of scrambler errors.
Detects and reports all the errors in Ethernet and CPRI layer
Glitch insertion and detection.
Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Supports constraints Randomization.
Status counters for various events on bus.
Supports bus accurate timing and timing checks.
Callbacks in Master, Slave and Monitor for user processing of data.
eCPRI Verification IP comes with complete test suite to test every feature of eCPRI specification.
Functional coverage for complete eCPRI features.

Benefits

Faster testbench development and more complete verification of eCPRI designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the eCPRI testcases.
Examples showing how to connect various components, and usage of Master,Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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