The CMS0041 DVB-T2 Modulator provides all the necessary processing steps to modulate single transport stream into a complex I/Q signal for input to a pair of DACs, or interpolating DAC devices such as the AD9857/AD9957 or RF DACs such as the AD9789. Optionally the output can be selected as an IF to supply a single DAC.
Additional extension cores are available for multiple PLP (common/data) support, T2MI interface support and SFN deployment support.
The design has been optimised to provide excellent performance in low cost FPGA devices such as the Cyclone range from Altera or the Spartan range from Xilinx.
A description of the processing steps follows:
TS Processing. The TS processing block performs rate adaptation functions in Broadcast applications to ensure that variable transmission delays do not result in disturbances of time-critical services such as audio and video. Both normal-mode and High Efficiency-Mode(HEM) processing is supported.
Null packet deletion. The Null packet deletion block removes null TS packets from the input stream to maximise the capacity available for information services in VCM and ACM modes. The mechanism defined by DVB-T2 allows for complete restoration of the input stream where null packets are necessary to maintain a constant delay.
CRC-8 Encoding. An 8-bit CRC is added to each outgoing TS packet and serves to allow packet-level error detection at the receiver.
Baseband buffer and Padding. The baseband padding block inserts a fixed-length Baseband Header at the start of each BBFRAME and pads to the end of the frame during ACM operation. The structure of the Baseband Header is as described in EN 302 755.
Baseband Scrambling. The baseband scrambler block performs the energy dispersal and transport multiplex adaptation using the DVB randomisation polynomial 1+x14+x15.
When processing L1-field frames (L1PRE/L1POST), zero padding is added to ensure the non-standard L1 frame length is compliant prior to FEC encoding.
BCH, LDPC Encoders. These blocks systematically encode each frame and append error correction information bits. When processing L1-field frames (L1PRE/L1POST), puncturing is performed where necessary following FEC encoding.
Bit Interleaver and Demux. The bit interleaver block applies block-based and column-twist bit interleaving to the coded frame prior to symbol de multiplexing and mapping.
Mapping and Rotation. This block performs the QAM constellation mapping using the mapping schemes specified by DVB for BPSK, QPSK, QAM16, QAM64 and QAM256. Optionally constellation rotation is applied as indicated by the L1FIELD information fields, together with L1-ACE modifications when enabled.
Cell and Timing Interleaving. This block performs both the cell and timing interleaving as dictated by the DVB-T2 specification. Typically, external memory, such as SDRAM, would be utilised for the substantial Timing interleaver storage required by the standard.
T2 Frame builder. The DVB-T2 specification details a frame and super-frame structure with scattered, continuous, tone-reservation and closing-symbol information inserted at various carriers within each OFDM symbol. This block manages the collation of data carriers from the various L1 & L2 encoded FECFRAMES based on the L1FIELD information fields. This block is also responsible for sequencing the appropriate OFDM symbol type information through to the subsequent pilot/guard insertion and IFFT processing stages.
Frequency interleaving and Pilot insertion. The DVB-T2 standard specifies a number of OFDM size dependent frequency interleaving modes together with various pilot patterns as indicated by the embedded L1FIELD information fields. This block is responsible for both the OFDM symbol frequency interleaving and also the subsequent insertion of the pilot carriers. Both SISO and MISO configurations are supported.
IFFT. This block performs the Inverse Fast Fourier Transform (IFFT) on the 1k, 2k, 4k, 8k, 16k or 32k carriers as indicated by the L1PRE field. A proprietary architecture is used which yields low Guassian noise, high MER outputs yet utilises low datapath widths. The IFFT also manages the on-air timing of the OFDM symbols by guard interval insertion (1/128, 19/256, 19/128, 1/32, 1/16, 1/8 or 1/4).
An optional windowing function is also included to reduce spurious emissions caused by the OFDM symbol transitions. A further optional in-band pre distortion can also be optionally performed.
Additionally, the DVB-T2 standard specifies a number of schemes to aid peak-to-average power reduction (PAPR) of the modulated signal. The Commsonic DVB-T2 core provides a number of techniques to utilise the hooks make available by the standard.
Resampler. This block re-samples the complex samples output from the IFFT into complex samples at the core clock frequency. This provides an ultra flexible clocking strategy. This block also scales automatically as required to satisfy the selected channel bandwidth (1·7MHz, 5MHz, 6MHz, 7MHz, 8MHz or 10MHz).
Baseband-to-IF. This block provides the option to mix the signal up to a higher IF as defined by a software register. This block may be removed using synthesis options if it is not required.
DAC Aperture Correction. This optional step provides compensation for the sin(x)/x (or SINC) distortion that is introduced in the DAC. This block may be removed using synthesis options is the feature is not required.
Radio Interface. This block performs some final, register-selectable processing functions to optimise the output for the radio in the target application. For example, the data can be formatted to work with either twos-complement or offset-binary DAC devices. In addition the data is formatted to suit the external vice that could take separate I/Q, multiplexed I/Q or a single IF output.
Additional modes are added to support the Analog Devices AD9857(or AD9957) device that provide up conversion, SINC filtering and DAC functions in a single package. The AD9857 device requires that the I/Q data be multiplexed onto a single data bus. The ad9857_pdclk input is provided to enable this feature and should be sourced from the AD9857 PDCLK output.
Register Bank. The register bank provides a simple 32-bit interface for reading and writing registers within the modulator block. Additionally the 32-bit interface is used to access the two external memories (TITL and IFFT) where necessary. Full details of the available registers and control configuration for the modulator core are contained within the full IP guide for the core.
