DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications
Overview
Synopsys has a long history of working with DSP customers to meet the ever-increasing computation requirements, offering lowest power consumption for embedded applications. These include wide deployment in wireless communications baseband modem SoC devices, industrial automation, automotive powertrain applications, radar and LiDAR. ARC Processors, coupled with a comprehensive portfolio of IP and tools, provide everything needed to design signal processing SoCs. There are four ARC DSP product lines: EMxD, HS4xD, HS57D and VPX.
Key Features
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
Benefits
- ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed.
- The ARChitect wizard enables drag-and-drop configuration of the core, including options for Instruction, program counter and loop counter widths
- Register file sizeTimers, reset and interrupts Byte ordering Memory type, size, partitioning, base address Power management, clock gating Ports and bus protocol Multipliers, dividers and other hardware features Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT).
- Adding/removing instructions
Technical Specifications
Maturity
Available on request
Availability
Available
Related IPs
- Multifunctional DSP Architecture for High-Performance, Low-Power Audio/Voice/Sensing and Wireless Communication Applications
- ARC VPX DSPs are VLIW/SIMD processors optimized for highly parallel processing with minimal energy and area consumption for a range of embedded workloads
- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications
- Compact ARC EM Processors feature excellent code density, small size, and ultra-low power consumption for power-sensitive, area-critical embedded applications
- ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications