Dolphin GPIO Controller
Overview
Dolphin Technology provides General Purpose I/O IP which cosists of up to 32 I/O ports that can be programmed individually for input, output, or bidirectional operation. Each port can be programmed to trigger the GPIO interrupt on level (high, low) or edge (rising, falling, any) events. The IP serves as additional means of communication between various components of the system on chip (SoC).
Key Features
- Dolphin GPIO Controller supports:
- Programmable number of GPIO signals which is input, output or bidirectional operation
- Programmable interrupt with some event types
- Bypass mode to control directly each GPIO port
- Support internal register to capture input or output data
- Support open drain and pull up/down option
- Clock synchronization
- Programmable FIFO watermarks
- Interrupt interface
- Software interface consistent with AMBA APB Bus, configurable bus width 8/16/32+
Benefits
- Compliant with the following specifications:
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Foundry, Node
TSMC 7;12;16;28;40;55;65;80;90nm
Maturity
Pre Silicon
Availability
Yes
TSMC
Pre-Silicon:
130nm
LV