DO-254 AXI to PCI Bridge 1.00a

Overview

Key Features

• Fully compatible 32-bit, 66/33 MHz Initiator/Target core for PCI™
• Customizable, programmable, single-chip solution
• Pre-defined implementation for predictable timing
• Incorporates Xilinx® Smart-IP technology
• 3.3V operation at 0?66 MHz
• Fully verified design tested with Xilinx proprietary test bench and hardware
• Delivered through the Xilinx® CORE Generator™ software
• CardBus compliant
• Supported initiator functions:
• ? Configuration read, configuration write
• ? Memory read, memory write, MRM, MRL User Guide v3
• ? Interrupt acknowledge, special cycles VHDL/Verilog Simulation Model
• ? I/O read, I/O write
• Supported target functions:
• ? Type 0 configuration space header
• ? Up to three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB)
• ? Medium decode speed
• ? Parity generation, parity error detection
• ? Configuration read, configuration write
• ? Memory read, memory write, MRM, MRL
• ? Interrupt acknowledge
• ? I/O read, I/O write
• ? Target abort, target retry, target disconnect

Benefits

• Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.

Deliverables

• Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.

Technical Specifications