DO-254 AXI Interconnect

Overview

Key Features

• Key features in EDK:
• Selectable interconnect architecture
• Crossbar mode (Performance optimized): Shared-Address, Multiple-Data (SAMD) crossbar architecture with parallel pathways for write and read data channels
• Shared Access mode (Area optimized): Shared write data, shared read data, and single shared address pathways
• AXI protocol compliant (AXI3, AXI4, and AXI4-Lite) includes:
• Burst lengths up to 256 for incremental (INCR) bursts
• Converts AXI4 bursts > 16 beats when targeting AXI3 slave devices by splitting transactions
• Generates REGION outputs for use by slave devices with multiple address decode ranges
• Propagates USER signals on each channel, if any; independent USER signal width per channel (optional)
• Propagates Quality of Service (QoS) signals, if any; not used by the AXI Interconnect core (optional)
• Interface data widths:
• AXI4: 32, 64, 128, 256, 512, or 1024 bits
• AXI4-Lite: 32 bits
• 32-bit address width
• Connects to 1-16 master devices and to 1-16 slave devices
• Built-in data-width conversion, synchronous/ asynchronous clock-rate conversion and AXI4-Lite/AXI3 protocol conversion
• Optional register-slice pipelining and datapath FIFO buffering
• Optional packet-FIFO capability
• Delays issuing AWVALID until the complete burst is stored in the write data FIFO
• Delays issuing ARVALID until the read data FIFO has enough vacancy to store the entire burst length
• Supports multiple outstanding transactions in crossbar mode
• “Single-Slave per ID” method of cyclic dependency (deadlock) avoidance
• Fixed priority and round-robin arbitration
• Supports TrustZone security for each connected slave as a whole
• Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization
• Key features in CORE Generator:
• AXI protocol compliant (AXI4 only), including:
• Burst lengths up to 256 for incremental (INCR) bursts
• Propagates Quality of Service (QoS) signals, if any; not used by the AXI Interconnect core (optional)
• Interface data widths:32, 64, 128, 256, 512, or 1024 bits
• Address width: 12 to 64 bits
• Connects to 1-16 master devices and to one slave device
• Built-in data-width conversion and synchronous /asynchronous clock-rate conversion
• Optional register-slice pipelining and datapath FIFO buffering
• Optional packet-FIFO capability
• Delays issuing AWVALID until the complete burst is stored in the write data FIFO
• Delays issuing ARVALID until the read data FIFO has enough vacancy to store the entire burst length
• Supports multiple outstanding transactions
• Fixed priority and round-robin arbitration
• Support for Read-only and Write-only master devices, resulting in reduced resource utilization

Benefits

• Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.

Deliverables

• Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.

Technical Specifications