DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process
Overview
An ADDLL operate at 5MHz~70MHz.Output produce a rising/falling edge delay tuning clock.UMC 40nm LP/RVT Logic process.
Technical Specifications
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
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