Display Controller - LCD / OLED Panels (AHB-Lite Bus)

Overview

The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to a TFT LCD panel. In an FPGA, ASIC, or ASSP device, the microprocessor is typically an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.

The DB9000AHB-Lite can connect directly to a multi-port memory controller with an AHB-Lite port interface.

Key Features

Wide range of programmable LCD Panel resolutions:
- 320x200, 320x240,
- 640x200, 640x240, 640x400, 640x480
- 800x600, 1024x768, 1280x1024
Support for 1 Port TFT LCD Panel interfaces:
- 18-bit digital (6-bits/color) & 24-bit digital (8-bits/color)
Programmable frame buffer bits-per-pixel (bpp) color depths:
- 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel
- 16, 18, bpp directly drive 18-bit LCD pixel
- 24 bpp directly drive 24-bit LCD pixel
Programmable Output format support:
- RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface
- RGB 8:8:8 on 24-bit digital interface
Programmable horizontal timing parameters:
- horizontal front porch
- horizontal back porch
- horizontal sync width
- horizontal pixels-per-line
Programmable vertical timing parameters:
- vertical front porch
- vertical back porch
- vertical sync width
- vertical lines-per-panel
Programmable polarity of timing signals:
- vertical sync polarity
- horizontal sync polarity
- pixel clock polarity
- display enable polarity
Three memories:
- 16-word x 32 bit input FIFO, decoupling AHB bus & LCD panel clock rates. Integrated with DMA controller.
- 256-word x 16-bit Color Palette RAM
- 16-word output FIFO
- FIFOs parameterizable in depth and width
Power up and down sequencing support
9 sources of internal interrupts with masking control
Little-endian, big-endian, or Windows CE mode
Compliance with AMBA Specification (Rev 2.0)
Fully-synchronous, synthesizable Verilog or VHDL RTL core.

Block Diagram

Deliverables

Verilog or VHDL RTL Source or technology-specific netlist.
Comprehensive testbench suite with expected results.
Synthesis scripts.
Installation & Implementation Guide.
Technical Reference Manual.

Technical Specifications

Foundry, Node

Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC, Global Foundaries

Maturity

Successful in Company SoC Demo Reference Design & Customer Implementations

Availability

Immediately

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