Display Controller - LCD / OLED Panels (AHB-Lite Bus)

Overview

Key Features

• Wide range of programmable LCD Panel resolutions:  
  •  Maximum programmable resolutions of 4096x4096 
  •  Horizontal pixel resolutions from 16 to 4096 pixels in 16 pixel increments. 
• Example LCD Panel high resolutions: 
  •  4096x2560, 3840x2160, 2560x2048, 2048x2048, 2048x1536,  1920x1200, 1920x1080, 1680x1050, 1600x1200 
  •  1600x900, 1440x900, 1366x768, 1280x1024, 1280×768, 1080x1920, 1024x768, 1024x600, 1024x576, 960x540, 800x600, 800x480 
• Example LCD Panel medium / small resolutions: 
  •  640x480, 640x400, 640x240, 640x200, 480x800, 480x640, 480x272  
  •  480x234, 240x400, 240x320, 240x240, 320x200, 320x240 
• Support for 1 Port TFT LCD Panel interfaces: 
  •  18-bit digital (6-bits/color) & 24-bit digital (8-bits/color) 
• Programmable frame buffer bits-per-pixel  (bpp) color depths:  
  •  1, 2, 4, 8    bpp mapped through Color Palette to 18-bit LCD pixel 
  •  16, 18,       bpp directly drive 18-bit LCD pixel 
  •  24              bpp directly drive 24-bit LCD pixel 
• Color Palette RAM to reduce Frame Buffer memory storage requirements and AHB Bus bandwidth: 
  •  256 entry by 16-bit RAM, implemented as 128 entry by 32-bits 
  •  Loaded via the Slave Bus Interface statically by the microprocessor or the Master Bus Interface dynamically with each frame by the DMA controller 
• Programmable Output format support: 
  •  RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface 
  •  RGB 8:8:8 on 24-bit digital interface 
• Programmable horizontal timing parameters: 
  •  horizontal front porch, back porch, sync width, pixels-per-line 
  •  horizontal sync polarity 
• Programmable vertical timing parameters: 
  •  vertical front porch, back porch, sync width, lines-per-panel 
  •  vertical sync polarity 
• Programmable pixel clock:  
  • pixel clock divider from 1 to 128 of Bus Clock 
  •  pixel clock polarity 
• Programmable Data Enable timing signal:  
  •  Derived from horizontal and vertical timing parameters 
• display enable polarity
• Three memories: 
  •  16-word x 32 bit input FIFO, decoupling AHB bus & LCD panel clock rates. Integrated with DMA controller. 
  •  256-word x 16-bit Color Palette RAM 
  •  16-word output FIFO 
  •  FIFOs parameterizable in depth and width 
• Optional Features: Overlay Windows, Color Space Conversion, Alpha Blending, Hardware Cursor 
• Power up and down sequencing support 
• 9 sources of internal interrupts with masking control 
• Little-endian, big-endian, or Windows CE mode 
• Compliance with AMBA 3.0 AHB-Lite Protocol Specification (v 1.0) 
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states.

Block Diagram

Deliverables

• Verilog or VHDL RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.

Technical Specifications