Digital Standard Cell Library

Overview

The agileDSCL is a compact Digital Standard Cell Library customizable for specific foundries and processes, and optimized for low-power, ultra-low-leakage, high-density or high-speed applications. It provides a selection of standard cells with functionalities essential to implement digital designs, with an additional power management library to support the implementation of low-power designs.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key Features

Compact standard cell library targeting a wide range of foundries and processes
Customized for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
- Multiple VT and channel length
- Thick-Oxide based cells
- Various track heights
Power Management library for low-power designs
Timing models for customizable range of PVT
High Quality library with class leading validation and models compatible with industry standard tools

Benefits

Optimised for PPA targets / DFM
- DFM-optimized
Customization
- Agile Analog’s COMPOSA tool enables efficient creation of libraries for specific foundries, processes, and cell architectures.
- Possibility to generate models at customized PVT corners

Applications

IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

Datasheet
Testing and Integration Guide
Verilog Models
Floorplan (LEF)
Timing models (LIB)
Netlist (CDL)
Layout (GDS)
Physical Verification Report
Design Report

Technical Specifications

Foundry, Node

Intel

Intel Foundry

Pre-Silicon: 16nm

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