The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data.
Digital FIR filter with APB interface
Overview
Key Features
- Programmable decimation filter rate between 1 and 4.
- Programmable number of taps between 3 and 64.
- Programmable 16-bit coefficients.
- 16-bit data
- A new filter output is available every “TAPS” clock cycles.
- Scaling and rounding of filter output to 22 bits.
- No requirement for symmetric or anti-symmetric filters
- AMBA APB control register interface
- DMA data interface
Benefits
- Very low resource requirements
- Within +/-1 LSB of floating point reference model
Deliverables
- RTL source code
- Testbench with various stimulus generation
- Synthesis scripts
- MATLAB model
Technical Specifications
Foundry, Node
Any
Maturity
Mature
Availability
Now
Related IPs
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- Distributed Arithmetic FIR (DA-FIR) Filter Generator
- Spacewire Codec with AHB host interface
- Multi-Rate Serial Digital Interface (SDI) PHY Layer
- Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY)
- 2D FIR Filter