Digital Down Converter core

Overview

The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource efficient way achieving a 16x table compression. The core has an APB interface to set the frequency and phase and the data path uses AXI4-Stream interfaces for simple connectivity.

Key Features

Parameterizable core with these defaults
24-bit phase accumulator
4096 entry (equivalent) sine/cosine table
10-bit sine/cosine table amplitude quantization
16-bit input/output data
APB interface for the control plane
AXI4-Stream interface for the data plane

Benefits

Standard interfacing
Highly compressed DDS table
Replaces FPGA vendor IP when doing an FPGA to ASIC migration
ASIC and FPGA target neutral

Applications

Remote Radio Heads (RRH)
MIMO Beamformers for 5G
Front-end for Software Defined Radios (SDR)

Deliverables

RTL
Testbench
Synthesis scripts
Documentation
MATLAB and C++ bit exact model

Technical Specifications

Availability

Now

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