The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption. The model is fully compliant with FIPS46-2.
DES Encryption and Decryption Processor
Overview
Key Features
- Fully compliant 56-Bit key DES implementation
- Single DES operation
- Encryption and decryption are performed in 16 clock cycles
- Suitable for ECB, CBC, CFB and OFB implementations
- Suitable for Triple-DES implementation
- No dead clock cycles
- Simple interface and timing
- Fully synchronous design
Technical Specifications
Availability
Now
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