DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor

Overview

The Triple DES Coprocessor is a Data Encryption Standard (FIPS 46-3) peripheral computing DES and Triple DES (TDES and 3DES) encryption and decryption through a highly-optimized secure architecture. Based on 2.5 kgates, the Triple DES Coprocessor computes DES and 3DES in 16 and 48 cycles respectively.

Key Features

DES and TDES decryption and encryption
three implementations available: one key optimized; two keys optimized; three keys optimized
Akkar & Giraud secure implementation
gate count smaller than 2.5 kgates
DES and TDES computation in 16 and 48 cycles, respectively
"start-on-key" and "start-on-data" configurations speed-up execution time
protected register access (intermediate results not accessible)
straightforward integration through AMBA APB 3.0 bus (customized on request)

Benefits

FIP 46-3 compliant
Three versions available
Small gate count
Protected register access
Silicon proven

Deliverables

VHDL source codes
VHDL testbenches
Synopsys synthesis scripts
C integration tests
design specification

Technical Specifications

Maturity

Silicon proven

Availability

Available

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