Denali DDR PHY for TSMC

Overview

LPDDR4/3, DDR4/3/3L, up to 4266Mbps

The latest Denali high-speed DDR PHY IP is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The application-optimized DDR PHY IP can achieve speeds up to 4266Mbps. Low-power features include the addition of VDD low-power idle state in the PHY, and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce the overall area by up to 20%. The DDR PHY IP is developed by experienced teams with industry-leading domain expertise and is extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoC and is verified with the Denali controller IP for DDR as part of a complete memory subsystem solution. The Denali DDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.

Key Features

Application optimized configurations for fast time to delivery and lower risk
Memory controller interface complies with DFI standards up to 5.2
Internal and external datapath loop-back modes
Per-bit deskew on read and write datapath
Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
I/O pads with impedance calibration logic and data retention capability
RX and TX equalization for heavily loaded systems
Fine-grain custom delay cell for delay tuning

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

GDSII macros with abstract in LEF
Verilog post-layout netlist
STA scripts for use at chip or standalone PHY levels
Liberty timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

TSMC 16nm, 28nm

Maturity

Available on request

TSMC

Pre-Silicon: 16nm , 28nm

Request Info