DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 90nm 90G,GT,LP
Overview
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 3.1 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
Technical Specifications
Foundry, Node
TSMC 90nm
Maturity
Pre Silicon
Availability
Available
TSMC
Pre-Silicon:
90nm
FS
,
90nm
FT
,
90nm
G
,
90nm
GOD
,
90nm
GT
,
90nm
LP
,
90nm
zzz
Related IPs
- 2.5V DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 0.13um LV,LVOD
- DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF
- DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 65nm 65GP,LP,LP_EMF
- DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 80nm 80GC,LP_EMF
- DDRI/II/III SSTL/HSTL combo interface without RTT (rectangle) - TSMC 90nm 90G,GT,LP
- DDRI/II/III SSTL/HSTL combo interface with RTT (square) - TSMC 90nm 90G,GT,LP