2.5V DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 0.13um LV,LVOD
Overview
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 3.1 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
Applications
- Memory Controller
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Foundry, Node
TSMC 130nm CL013LV
Maturity
Pre Silicon
Availability
Available
TSMC
Pre-Silicon:
130nm
,
130nm
BCD
,
130nm
BCD+
,
130nm
G
,
130nm
LP
,
130nm
LV
,
130nm
LVOD
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