DDR5/4 PHY for Samsung

Overview

Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area

The latest, the DDR5/4 PHY IP for Samsung 7nm, is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The applicationoptimized DDR PHY IP can achieve speeds up to 4800Mbps. Low-power features include the addition of a VDD low-power idle state in the PHY and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce the overall area by up to 20%. The DDR PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Cadence Denali Controller IP for DDR as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.

Key Features

Application optimized configurations for fast time to delivery and lower risk
Memory controller interface complies with DFI standards up to 5.0
Internal and external datapath loop-back modes
Per-bit deskew on read and write datapath
Low-power VDD idle, VDD light sleep, and powerefficient clocking in low-speed modes
I/O pads with impedance calibration logic and data retention capability
RX and TX equalization for heavily loaded systems
Fine-grain custom delay cell for delay tuning

Block Diagram

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

STA scripts for use at chip or standalone PHY levels
Liberty timing model
SDF for back-annotated timing verification
Verilog models of I/O pads, and RTL for all PHY modules
Verilog testbench with memory model, configuration files, and sample tests

Technical Specifications

Foundry, Node

Samsung 7nm

Maturity

Available on request

Samsung

Pre-Silicon: 7nm

Request Info