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DDR4 RCD Memory Model

Overview

DDR4 RCD Memory Model provides an smart way to verify the DDR4 RCD component of a SOC or a ASIC. The SmartDV's DDR4 RCD memory model is fully compliant with standard DDR4 RCD Specification and provides the following features. Better than Denali Memory Models.

DDR4 RCD Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 RCD Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports DDR4 RCD devices from all leading vendors. Supports 100% of DDR4 RCD protocol standard JESD82-31A.
  • Supports all speed grades as per specification. Quickly validates the implementation of the DDR4 RCD standard JESD82-31A.
  • Supports DDR4 command and address bus transmission as per DDR4 standard JESD79-4C.
  • Supports parity.
  • Supports following CS operating mode
    • Direct CS Mode
    • Quad CS Mode
    • Encoded Quad CS Mode
  • Supports Dual Frequency.
  • Supports following power down modes
    • Register CKE Power Down
    • Clock Stopped Power Down
  • Supports for data buffer control commands.
  • Supports Output Inversion Enable/Disable.
  • Supports Latency Equalization Support.
  • Supports Output Delay Control.
  • Supports Output Slew Rate Control.
  • Supports Transparent Mode.
  • Supports Control Gear-Down Mode.
  • Supports Handling of Parity Errors.
  • Supports all control word programming.
  • Supports CA bus training.
  • Supports Multi-purpose register.
  • Supports Optional NVDIMM Features
    • Save mode Entry/Exit sequences
    • Restore Mode Entry/Exit sequences
    • Supports LCOM[2:0] Command Frames
    • Supports LCOM[1:0] Read Data Frames
    • Supports LCOM[1:0] Asynchronous Interrupt
    • Control word access protection
  • Checks for following
    • Check-points include power up initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports input clock stop and frequency change.
  • Protocol checker fully compliant with DDR4 RCD Specification JESD82-31A.
  • Constantly monitors DDR4 RCD behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing violations and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of DDR4 RCD designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

DDR4 RCD Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the DDR4 RCD testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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