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DDR4 multiPHY SP - SS 14LPP

Overview

The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAM memories. The DDR4 multiPHY IP supports DDR4 SDRAM speeds from DDR4-1333 through DDR4-2667, DDR3 SDRAM speeds from DDR3-666 to DDR3-2133, LPDDR2 SDRAMs from 0 to 1066 Mbps and LPDDR3 SDRAMs from 0 to 2133 Mbps. The DDR4 multiPHY IP cores are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR4 multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single address/command macro block, multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width, and separate PLL macrocells that directly abut to the address/command macro block and data macro blocks.

A key component of the DDR4 multiPHY is the extensive in-system data training/calibration capability used to maximize the overall timing budget and improve system reliability. The DDR4 multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling. The DDR4 multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR3 SDRAMs and VREF level training for DDR4 SDRAMs.

Key Features

  • Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
    • Including support for DDR3L (1.35V) and DDR3U (1.25V) SDRAMs
  • When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR4/DDR3/LPDDR2/LPDDR3 interface IP solution
  • Compatible with the Synopsys DDR PHY Compiler
    • GUI-based tool used to assemble a customized DDR PHY targeting a specific application
  • Support for key DDR4 features including:
    • POD_12 I/O for DDR4
    • Data bus inversion (DBI)
    • VREFDQ training
    • CA parity
  • Scalable architecture that supports data rates up to DDR4-2667
  • Support for DIMMs
  • Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
  • Low latency
  • PHY Utility Bock (PUBM3) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR4 multiPHY
  • DFI 3.1 compliant interface
  • Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
  • Permits operating with SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
  • Support for 1 to 4 memory ranks
  • PHY-Controller interface runs in 1:1 or 1:2 mode (ratio of application bus clock to SDRAM clock), simplifying core logic timing constraints
  • Includes the PLL and all timing circuits necessary to meet timing specifications
  • Write leveling timing circuits to compensate address and control versus data delays
  • Write and read bit timing circuits compensate per-bit delay skew of individual data bits within each data byte
  • Per-bit deskew of the address/command bus for LPDDR3 SDRAMs
  • Locally calibrated timing circuits minimize OCV and ACLV effects, and accommodate voltage or temperature change induced timing drift
  • Area-optimized I/O
    • 6 layers of metal
    • 25um I/O pitch for 28nm
    • Supports circuit under pad (CUP) and bond over active (BOA)
    • Supports flip chip and wire bond
  • I/O retention mode
    • Maintains I/O drive state during VDD power down
    • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
  • Accommodates any poly orientation in 28nm processes and below allowing the DDR4 multiPHY to go around a corner if required
  • Advanced testability
    • At-speed loopback testing on both the address and data channels
    • Delay line oscillator test mode
    • MUX-scan ATPG
  • Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package, and printed circuit board environments

Block Diagram

DDR4 multiPHY SP - SS 14LPP Block Diagram

Technical Specifications

Foundry, Node
SS 14LPP
Samsung
Pre-Silicon: 14nm
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