DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)

Overview

The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L SDRAM interfaces operating at up to 3200 Mbps. LPDDR4 support is available in the Synopsys LPDDR4 multiPHY. The Synopsys DDR4/3 PHY is ideal for systems that require high-speed DDR3/ 4 performance requiring high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 16 ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility
Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded ARC® calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with Synopsys’ Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.

Key Features

Low latency, small area, low power
Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
Compatible with JEDEC standard DDR3 or DDR3L SDRAMs up to 2133 Mbps
DFI 4.0 compliant interface to the memory controller
I/Os include receiver decision feedback equalization (DFE) and driver feed-forward equalization (FFE)
PHY independent, firmware-based training using an embedded calibration processor
Can be trained for up to four distinct states/frequencies to permit fast frequency changes between the four frequencies
Three inactive idle states:
Voltage and temperature compensated delay lines used for:
Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation
Supports PHYs that go around a die corner
Support for 28-nm and below poly orientation rules
Includes the PHY Utility Block (PUB)
At-speed loopback testing on both the address and data channels
Delay line BIST
MUX-scan ATPG (stuck-at SCAN)
Firmware-based DDR4/3 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers

Benefits

Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
High-performance DDR PHY supporting data rates up to 3200 Mbps
PHY independent, firmware-based training using an embedded calibration processor
Supports up to 4 trained states/ frequencies with <5us switching time
I/O receiver decision feedback equalization and driver feed-forward equalization
VT compensated delay lines for DQS centering, read/write leveling, and per bit deskew
DFI 4.0-compliant controller interface
Designed for rapid integration with Synopsys memory or protocol controllers for a complete DDR interface solution

Applications

Data centers (networking and storage)
Servers
High-performance computing
Digital home
Digital office

Deliverables

Executable .run installation file, including GDSII, LEF Files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample verification environment, PHY data book, physical implementation guide, application notes, verification guide, installation guide, implementation checklist
The PHY Utility Block includes Verilog code, synthesis/STA constraints and scripts, sample verification environment, data book, binary image of firmware for training, and 2D eye mapping DFT
DDR PHY Compiler

Technical Specifications

Foundry, Node

Samsung 14nm, 11nm, 10nm, 8nm - LPP

Maturity

Available on request

Availability

Available

Samsung

Pre-Silicon: 8nm , 10nm , 11nm , 14nm

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