The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant with JESD79-3 specification. The DDR3 PHY IP provides the Industry standard DDR PHY Interface (DFI) bus at the local side to interface with the Memory Controller. The DFI protocol defines the signals, signal relationships, and timing parameters required to transfer control information and data to and from the DDDR3 devices over the DFI bus.
The DDR3 PHY IP reduces the effort required to integrate any DDR3 memory controller with Lattice FPGA’s DDR3 primitives and thereby enables the user to implement only the logical portion of the memory controller in the user design. The Lattice’s DDR3 PHY IP contains all the logics required for Memory device initialization procedure, Write leveling, Read data capture and Read data de-skew that are dependent on FPGA DDR IO primitives.
DDR3 PHY
Overview
Key Features
- Supports write leveling for each DQS group. Option to switch off write leveling for On-board memory applications
- Supports all valid DDR3 commands
- Supports dynamic On-Die Termination (ODT) controls
- LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
- Option for controlling memory reset outside the IP core
- 1:1 frequency ratio interface between MC and DFI, 1:2 ratio between DFI and PHY
- Interfaces to any DDR3 Memory Controller (MC) through DDR PHY Interface (DFI) industry specification
- Interfaces to industry standard DDR3 SDRAM components and modules compliant with JESD79-3 specification
- Support for all LatticeECP3 “EA” devices
- High-Performance DDR3 operations up to 400 MHz/800 Mbps
- Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
- Supports x4, x8, and x16 device configurations
- Supports one unbuffered DDR3 DIMM or DDR3 RDIMM module with up to two ranks per DIMM
- Supports on-board memory (up to two chip selects)
- Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
- Supports automatic DDR3 SDRAM initialization with user mode register programming
Block Diagram
