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DDR3 Memory Model

Overview

DDR3 Memory Model provides an smart way to verify the DDR3 component of a SOC or a ASIC. The SmartDV's DDR3 memory model is fully compliant with standard DDR3 Specification and provides the following features. Better than Denali Memory Models.

DDR3 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR3 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports DDR3 memory devices from all leading vendors.
  • Supports 100% of DDR3 protocol standard JESD79-3F.
  • Supports all the DDR3 commands as per the specs.
  • Supports upto 8 GB device density.
  • Supports 8 internal banks.
  • Supports the following devices.
    • X4
    • X8
    • X16
  • Supports all speed grades as per specification.
  • Quickly validates the implementation of the DDR3 standard JESD79-3F.
  • Supports Programmable Write latency and Read latency.
  • Supports On-the-fly for burst length.
  • Supports Programmable burst lengths: 4,8.
  • Supports the following burst order.
    • Sequential
    • Interleave
  • Checks for following
    • Check-points include power up, initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports for All Mode registers programming.
  • Supports for Write data Mask.
  • Supports for Power Down features.
  • Supports for input clock stop and frequency change.
  • Supports for DLL.
  • Supports for Write leveling.
  • Supports for ZQ Calibration.
  • Supports for automatic self refresh.
  • Supports for self refresh mode.
  • Supports for ODT(On-Die Termination).
  • Supports for full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Protocol checker fully compliant with DDR3 Specification JESD79-3F.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Constantly monitors DDR3 behavior during simulation.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of DDR3 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

DDR3 Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the DDR3 testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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