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DDR multiPHY IP

Overview

The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.25V DDR3), DDR2, LPDDR, and LPDDR2 SDRAM memories up to 1066 Mbps data rates. The DDR multiPHY is an area- and feature-optimized PHY that is ideal for designers who require flexibility in regard to the type and number of DDR interfaces for their SoCs. Once implemented in the chip, the DDR multiPHY allows the specific DDR type supported in a system to be programmed via simple software control.

The DDR multiPHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a DLL library, and the unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based controller logic and the hard PHY IP.

The DDR multiPHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching. A key component of the DDR multiPHY is the PHY Utility Block (PUBL) that is supplied as soft IP. The PUBL contains the circuitry to provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.

Key Features

  • Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
  • When combined with a Synopsys Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
  • Compatible with the Synopsys DDR PHY Compiler
  • GUI-based tool used to assemble a customized DDR PHY targeting a specific application
  • Scalable architecture that supports from 0 to 1066 Mbps
  • DFI 2.1 interface to controller
  • Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, delay locked loops (DLLs) and Interface Timing Module (ITM) libraries
    • All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.), while simultaneously taking all the difficult timing closure out of the user's hands.
  • Support for package on package (PoP) designs
    • The PHY can be broken up and distributed around the die if required for PoP connectivity
  • Uses only 4 layers of metal for ITM and DLL
  • Uses only 6 layers of metal for I/O cells
  • Low latency
  • Precision analog DLLs results in ultra-low jitter
    • DLL component for SDRAM command generation and general host timing
    • DLL component for SDRAM write data generation and read data capture
    • Immune to PVT variation
    • Uses core voltage level
  • Real time DQS drift detection and compensation
  • Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
  • Permits operating with SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
  • At-speed loopback test mode for production test
  • Low area and low power architecture
  • Application specific multi-protocol DDR I/O library featuring PVT independent ZQ/RZQ programmable ODT and drive strength
    • Includes calibration controller logic
    • Includes power, spacer, and corner cells
  • Area-optimized I/O
    • Staggered I/O supported
    • Supports circuit under pad (CUP) and bond over active (BOA)
    • Supports flip chip and wire bond
  • I/O retention mode
    • Maintains I/O drive state during VDD power down
    • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
  • Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments

Block Diagram

DDR multiPHY IP Block Diagram

Technical Specifications

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